1. Field of the Invention
The present invention relates to a production method for a semiconductor device, and more particularly to a production method for an SGT (Surrounding Gate Transistor) which is a vertical MOS transistor comprising a pillar-shaped semiconductor layer having a sidewall serving as a channel region, and a gate electrode formed to surround the channel region.
2. Description of the Related Art
With a view to achieving higher integration and higher performance of a semiconductor device, an SGT (Surrounding Gate Transistor) has been proposed which is a vertical transistor comprising a pillar-shaped semiconductor layer formed on a surface of a semiconductor substrate, and a gate formed to surround a sidewall of the pillar-shaped semiconductor layer (see, for example, the following Patent Document 1: JP 2-188966A). In the SGT, a drain, a gate and a source are arranged in a vertical direction, so that an occupancy area can be significantly reduced as compared with a conventional planar transistor.
FIG. 20(a) shows a top plan view of a CMOS inverter constructed using the SGT disclosed in the Patent Document 1, and FIG. 20(b) is a sectional view taken along the cutting-plane line A-A′ in the top plan view of FIG. 20(a).
Referring to FIGS. 20(a) and 20(b), an N-well 302 and a P-well 303 are formed in an upper region of a Si substrate 301. A pillar-shaped silicon layer 305 constituting a PMOS (PMOS pillar-shaped silicon layer 305) and a pillar-shaped silicon layer 306 constituting an NMOS (NMOS pillar-shaped silicon layer 306) are formed on a surface of the Si substrate, specifically, on respective ones of the N-well region and the P-well region, and a gate 308 is formed to surround the pillar-shaped silicon layers. Each of a P+ drain diffusion layer 310 formed underneath the PMOS pillar-shaped silicon layer, and a N+ drain diffusion layer 312 formed underneath the NMOS pillar-shaped silicon layer, is connected to an output terminal Vout. A source diffusion layer 309 formed on a top of the PMOS pillar-shaped silicon layer is connected to a power supply potential Vcc, and a source diffusion layer 311 formed on a top of the NMOS pillar-shaped silicon layer is connected to a ground potential Vss. The common gate 308 for the PMOS and the NMOS is connected to an input terminal Vin. In this manner, the CMOS inverter is formed.
A process flow as one example of an SGT production method is disclosed in the following Non-Patent Document 1. FIGS. 21(a) to 21(h) schematically show the process flow for forming a pillar-shaped silicon layer and a gate electrode of an SGT, in the Non-Patent Document 1. With reference to FIGS. 21(a) to 21(h), the process flow will be described below. As shown in FIG. 21(b), a silicon substrate 402 illustrated in FIG. 21(a) is prepared, and etched to form a pillar-shaped silicon layer 403. Then, as shown in FIG. 21(c), a gate dielectric film 404 is formed. Then, as shown in FIG. 21(d), a gate conductive film 405 is formed. Then, as shown in FIG. 21(e), the gate conductive film 405, and a portion of the gate dielectric film 404 on a top of the pillar-shaped silicon layer, are polished by chemical mechanical polishing (CMP). Then, as shown in FIG. 21(f), the gate conductive film 405 is etched back to allow the gate conductive film 405 surrounding the pillar-shaped silicon layer to have a desired gate length. Then, as shown in FIG. 21(g), a resist 406 for a gate line pattern is formed by lithography. Then, as shown in FIG. 21(h), the gate conductive film 405 is etched to form a gate electrode and a gate line.
However, the SGT production method illustrated in FIGS. 21(a) to 21(h) has the following problems.
Firstly, in the above process flow, dry etching for the pillar-shaped silicon layer has to be performed under etching conditions including a designated etching time, because it is unable to employ an end-point detection process based on monitoring of a change in plasma emission intensity. In this case, a height dimension of the pillar-shaped silicon layer is directly influenced by an etching rate of an etching apparatus during an etching operation, so that it will considerably fluctuate. In an SGT, a fluctuation in height dimension of a pillar-shaped silicon layer has a direct impact on a fluctuation in channel length, which causes a considerable fluctuation in transistor characteristics.
Secondly, in the above process flow, dry etching for a gate electrode also has to be performed under etching conditions including a designated etching time, because it is unable to employ the end-point detection process based on monitoring of a change in plasma emission intensity. In this case, a gate length is directly influenced by an etching rate of an etching apparatus during an etching operation, so that it will considerably fluctuate. The fluctuation in gate length inevitably causes a considerable fluctuation in transistor characteristics.
Thus, in the above SGT production method, due to considerable influence of the etching rate during the etching operation on the height dimension and the gate length of the pillar-shaped silicon layer, it is extremely difficult to minimize a fluctuation in transistor characteristics between wafers or production lots.
In view of the above circumstances, it is an object of the present invention to produce a semiconductor device while stabilizing a height dimension of a pillar-shaped semiconductor layer, and a gate length, by using an end-point detection process based on monitoring of a plasma emission intensity, during dry etching for forming the pillar-shaped semiconductor layer and during dry etching for setting the gate length.    Patent Document 1: JP 2-188966A    Non-Patent Document 1: Ruigang Li, et al., “50 nm Vertical Surrounding Gate MOSFET with S-Factor of 75 mV/dec”, Device Research Conference, 2001, p. 63